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features ? fast read access time ? 70 ns ? automatic page write operation ? internal address and data latches for 64 bytes ? internal control timer ? fast write cycle times ? page write cycle time: 3 ms or 10 ms maximum ? 1 to 64-byte page write operation ? low power dissipation ? 80 ma active current ? 3 ma standby current ? hardware and software data protection ? data polling for end of write detection ? high reliability cmos technology ? endurance: 10 4 or 10 5 cycles ? data retention: 10 years ? single 5v 10% supply ? cmos and ttl compatible inputs and outputs ? jedec approved byte-wide pinout ? full military and industrial temperature ranges ? green (pb/halide-free) packaging option 1. description the at28hc256 is a high-performance elec trically erasable and programmable read- only memory. its 256k of memory is organized as 32,768 words by 8 bits. manufac- tured with atmel?s advanced nonvolatile cmos technology, the at28hc256 offers access times to 70 ns with power dissi pation of just 440 mw. when the at28hc256 is deselected, the standby current is less than 5 ma. the at28hc256 is accessed like a static ram for the read or write cycle without the need for external components. the device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. during a write cycle, the address and 1 to 64 bytes of data are internally latched, freeing the addresses and data bus for other oper- ations. following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. the end of a write cycle can be detected by data polling of i/o7. once the end of a write cycle has been detected a new access for a read or write can begin. atmel?s 28hc256 has additional features to ensure high quality a nd manufacturability. the device utilizes internal error correction for extended endurance and improved data retention characteristics. an optional software data protection mechanism is available to guard against inadvertent wr ites. the device also includes an extra 64 bytes of eeprom for device identification or tracking. 256k (32k x 8) high-speed parallel eeprom at28hc256 0007n?peepr?9/09
2 0007n?peepr?9/09 at28hc256 2.1 28-lead tsop top view 2.2 28-lead pga top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 oe a11 a9 a8 a13 we vcc a14 a12 a7 a6 a5 a4 a3 a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 2.3 32-pad lcc, 32-lead plcc top view note: plcc package pins 1 and 17 are don?t connect. 2.4 28-lead cerdip/flatpack/soic ? top view 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a6 a5 a4 a3 a2 a1 a0 nc i/o0 a8 a9 a11 nc oe a10 ce i/o7 i/o6 4 3 2 1 32 31 30 14 15 16 17 18 19 20 i/o1 i/o2 gnd dc i/o3 i/o4 i/o5 a7 a12 a14 dc vcc we a13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 2. pin configurations pin name function a0 - a14 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect dc don?t connect
3 0007n?peepr?9/09 at28hc256 3. block diagram 4. device operation 4.1 read the at28hc256 is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state when either ce or oe is high. this dual-line control gives designers flexibility in prev enting bus contention in their system. 4.2 byte write a low pulse on the we or ce input with ce or we low (respectively) and oe high initiates a write cycle. the address is latc hed on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . once a byte write has been started it will automatically time itself to completion. once a programming operation has been initiated and for the duration of t wc , a read operation will effect ively be a polling operation. 4.3 page write the page write operation of the at28hc256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period . a page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. each successive byte must be written within 150 s (t blc ) of the previous byte. if the t blc limit is exceeded the at28c256 will cease accepting data and commence the internal programming operation. all bytes during a page write operation must reside on the same page as defined by the state of the a6 - a14 inputs. that is, for each we high to low transition dur- ing the page write operation, a6 - a14 must be the same. the a0 to a5 inputs are used to specify whic h bytes within the page are to be written. the bytes may be loaded in any order and may be altered within the same load period. only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. 4.4 data polling the at28hc256 features data polling to indicate the end of a write cycle. during a byte or page write cycle an atte mpted read of the last byte written will result in the complement of the written data to be presented on i/o7. once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. data polling may begin at anytime during the write cycle.
4 0007n?peepr?9/09 at28hc256 4.5 toggle bit in addition to data polling the at28hc256 provides anot her method for dete rmining the end of a write cycle. during the write operation, successive attempts to read data from the device will result in i/o6 toggling betw een one and zero. once the writ e has completed, i/o6 will stop toggling and valid data will be read. testing the toggle bit may begin at any time during the write cycle. 4.6 data protection if precautions are not taken, inadvertent writes to any 5-volt-only nonvolatile memory may occur during transition of the host system power supply. atmel ? has incorporated both hard- ware and software features that will protect the memory against inadver tent writes. 4.6.1 hardware protection hardware features protect against inadvertent writes to the at28hc256 in the following ways: (a) v cc sense ? if v cc is below 3.8v (typical) the wr ite function is inhibited; (b) v cc power-on delay ? once v cc has reached 3.8v the devic e will automatically time out 5 ms typical) before allowing a write; (c) write inhibit ? holding any one of oe low, ce high or we high inhibits write cycles; and (d) noise filter ? pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a write cycle. 4.6.2 software data protection a software controlled data protection feature has been implemented on the at28hc256. when enabled, the software data protection (sdp), will preven t inadvertent writes. the sdp feature may be enabled or disabled by the user; the at28hc256 is shipped from atmel with sdp disabled. sdp is enabled by the host system issuing a se ries of three write commands; three specific bytes of data are written to three specific addresses (refer to ?software data protection? algo- rithm). after writing the 3-byte command sequence and after t wc the entire at28hc256 will be protected against inadvertent write operations. it should be noted, that once protected the host may still perform a byte or page write to the at28hc256. this is done by preceding the data to be written by the same 3-byte command sequence. once set, sdp will remain active unless the disable command sequence is issued. power transitions do not disable sdp and sdp will pr otect the at28hc256 during power-up and power-down conditions. all command sequences must conform to the page write timing spec- ifications. it should also be noted that the data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. after setting sdp, any attempt to write to the device without the three byte command sequence will start the internal wr ite timers. no data will be writte n to the device; however, for the duration of t wc , read operations will effect ively be polling operations. 4.7 device identification an extra 64 bytes of eeprom me mory are available to the user for device identification. by raising a9 to 12v 0.5v and using address locations 7fc0h to 7fffh the additional bytes may be written to or read from in the same manner as the regular memory array. 4.8 optional chip erase mode the entire device can be erased using a 6-byte software code. please see ?software chip erase? application note for details.
5 0007n?peepr?9/09 at28hc256 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. 5. dc and ac operating range at28hc256-70 at28hc256-90 at28hc256-12 operating temperature (case) ind. -40c - 85c -40c - 85c -40c - 85c mil. -55c - 125c -55c - 125c v cc power supply 5v 10% 5v 10% 5v 10% 6. operating modes mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write inhibit v ih x (1) x high z write inhibit x x v ih write inhibit x v il x output disable x v ih x high z chip erase v il v h (3) v il high z 7. absolute maximum ratings* temperature under bias ............. .............. ..... -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability storage temperature ..................................... -65c to +150c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe and a9 with respect to ground ...................................-0.6v to +13.5v 8. dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc + 1v 10 a i lo output leakage current v i/o = 0v to v cc 10 a i sb1 v cc standby current ttl ce = 2.0v to v cc at28hc256-90, -12 3 ma at28hc256-70 60 ma i sb2 v cc standby current cmos ce = v cc - 0.3v to v cc at28hc256-90, -12 300 a i cc v cc active current f = 5 mhz; i out = 0 ma 80 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 6.0 ma 0.45 v v oh output high voltage i oh = -4 ma 2.4 v
6 0007n?peepr?9/09 at28hc256 10. ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. 9. ac read characteristics symbol parameter at28hc256-70 at28c256-90 at28hc256-12 units min max min max min max t acc address to output delay 70 90 120 ns t ce (1) ce to output delay 70 90 120 ns t oe (2) oe to output delay 0 35 0 40 0 50 ns t df (3)(4) ce or oe to output float 035040050ns t oh output hold from oe , ce or address, whichever occurred first 000ns
7 0007n?peepr?9/09 at28hc256 11. input test waveform s and measurement level 12. output test load note: 1. this parameter is characterized and is not 100% tested. t r , t f < 5 ns 13. pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
8 0007n?peepr?9/09 at28hc256 note: 1. nr = no restriction. 15. ac write waveforms 15.1 we controlled 15.2 ce controlled 14. ac write characteristics symbol parameter min max units t as , t oes address, oe setup time 0 ns t ah address hold time 50 ns t cs chip select setup time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )100ns t ds data setup time 50 ns t dh , t oeh data, oe hold time 0 ns t dv time to data valid nr (1)
9 0007n?peepr?9/09 at28hc256 17. page mode write waveforms (1)(2) notes: 1. a6 through a14 must specify the same page address during each high to low transition of we (or ce ). 2. oe must be high only when we and ce are both low. 18. chip erase waveforms 16. page mode write characteristics symbol parameter min typ max units t wc write cycle time (option available) at28hc256 5 10 ms at28hc256f 2 3 ms t as address setup time 0 ns t ah address hold time 50 ns t ds data setup time 50 ns t dh data hold time 0 ns t wp write pulse width 100 ns t blc byte load cycle time 150 s t wph write pulse width high 50 ns t s = t h = 5 sec (min.) t w = 10 msec (min.) v h = 12.0v 0.5v
10 0007n?peepr?9/09 at28hc256 19. software data protection enable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64 bytes of data are loaded. load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data xx to any address (4) load last byte to last address enter data protect state writes enabled (2) 20. software data protection disable algorithm (1) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 20 to address 5555 load data xx to any address (4) load last byte to last address load data 55 to address 2aaa exit data protect state (3) 21. software protected write cycle waveforms (1)(2) notes: 1. a6 through a14 must specify the same page address during each high to low transition of we (or ce ) after the software code has been entered. 2. oe must be high only when we and ce are both low.
11 0007n?peepr?9/09 at28hc256 notes: 1. these parameters are characterized and not 100% tested. 2. see ?ac read characteristics? on page 6 . 23. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see ?ac read characteristics? on page 6 . 25. toggle bit waveforms notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. 22. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 0 ns t oeh oe hold time 0 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns 24. toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns
12 0007n?peepr?9/09 at28hc256 26. normalized i cc graphs
13 0007n?peepr?9/09 at28hc256 27. ordering information 27.1 military dual marked package 27.1.1 at28hc256 t acc (ns) i cc (ma) ordering code package operation range active standby 90 80 0.3 at28hc256-90dm/883 5962-88634 03 xx 28d6 military/883c class b, fully compliant (-55 c to 125 c) at28hc256-90fm/883 5962-88634 03 zx 28f at28hc256-90lm/883 5962-88634 03 yx 32l at28hc256-90um/883 5962-88634 03 ux 28u 120 80 0.3 at28hc256-12dm/883 5962-88634 01 xx 28d6 at28hc256-12fm/883 5962-88634 01 zx 28f at28hc256-12lm/883 5962-88634 01 yx 32l at28hc256-12um/883 5962-88634 01 ux 28u package type 28d6 28-lead, 0.600" wide, non-windowed, ceramic dual inline package (cerdip) 28f 28-lead, non-windowed, ceramic bottom-brazed flat package (flatpack) 32l 32-pad, non-windowed, ceramic leadless chip carrier (lcc) 28u 28-pin, ceramic pin grid array (pga) options blank standard device: endurance = 10k write cycles; write time = 10 ms e high endurance option: endurance = 100k write cycles f fast write option: write time = 3 ms
14 0007n?peepr?9/09 at28hc256 note: 1. no dual marking for this device. 27.1.2 at28hc256e (1) t acc (ns) i cc (ma) ordering code package operation range active standby 90 80 0.3 at28hc256e-90dm/883 28d6 military/883c class b, fully compliant (-55 c to 125 c) at28hc256e-90fm/883 28f at28hc256e-90lm/883 32l at28hc256e-90um/883 28u 120 80 0.3 at28hc256e-12dm/883 28d6 at28hc256e-12fm/883 28f at28hc256e-12lm/883 32l at28hc256e-12um/883 28u 27.1.3 at28hc256f t acc (ns) i cc (ma) ordering code package operation range active standby 90 80 0.3 at28hc256f-90dm/883 5962-88634 04 xx 28d6 military/883c class b, fully compliant (-55 c to 125 c) at28hc256f-90fm/883 5962-88634 04 zx 28f at28hc256f-90lm/883 5962-88634 04 yx 32l at28hc256f-90um/883 5962-88634 04 ux 28u 120 80 0.3 at28hc256f-12dm/883 5962-88634 02 xx 28d6 at28hc256f-12fm/883 5962-88634 02 zx 28f at28hc256f-12lm/883 5962-88634 02 yx 32l at28hc256f-12um/883 5962-88634 02 ux 28u package type 28d6 28-lead, 0.600" wide, non-windowed, ceramic dual inline package (cerdip) 28f 28-lead, non-windowed, ceramic bottom-brazed flat package (flatpack) 32l 32-pad, non-windowed, ceramic leadless chip carrier (lcc) 28u 28-pin, ceramic pin grid array (pga) options blank standard device: endurance = 10k write cycles; write time = 10 ms e high endurance option: endurance = 100k write cycles f fast write option: write time = 3 ms
15 0007n?peepr?9/09 at28hc256 27.2 industrial green package option (pb/halide-free) 27.3 ordering information note previous datasheets included the low power suffixes l, le and lf on the at28hc256 for 120 ns and 90 ns speeds. the low power parameters are now standard; therefore, the l, le and lf suffixes are no longer required. 27.2.1 at28hc256 t acc (ns) i cc (ma) ordering code package operation range active standby 70 80 0.3 at28hc256-70ju 32j industrial (-40 c to 85 c) at28hc256-70su 28s at28hc256-70tu 28t 90 80 0.3 at28hc256-90ju 32j at28hc256-90su 28s at28hc256-90tu 28t 120 80 0.3 at28hc256-12ju 32j at28hc256-12su 28s at28hc256-12tu 28t 27.2.2 at28hc256e t acc (ns) i cc (ma) ordering code package operation range active standby 90 80 0.3 at28hc256e-90ju 32j industrial (-40 c to 85 c) at28hc256e-90su 28s at28hc256e-90tu 28t 120 80 0.3 at28hc256e-12ju 32j at28hc256e-12su 28s at28hc256e-12tu 28t 27.2.3 at28hc256f t acc (ns) i cc (ma) ordering code package operation range active standby 90 80 0.3 at28hc256f-90ju 32j industrial (-40 c to 85 c) at28hc256f-90su 28s at28hc256f-90tu 28t package type 32j 32-lead, plastic j-leaded chip carrier (plcc) 28s 28-lead, 0.300" wide, plastic gull wing small outline (soic) 28t 28-lead, plastic thin small outline package (tsop) options blank standard device: endurance = 10k write cycles; write time = 10 ms e high endurance option: endurance = 100k write cycles f fast write option: write time = 3 ms
16 0007n?peepr?9/09 at28hc256 27.4 die products contact atmel sales for die sales options.
17 0007n?peepr?9/09 at28hc256 28. packaging information 28.1 28d6 ? cerdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28d6 , 28-lead, 0.600" wide, non-windowed, ceramic dual inline package (cerdip) b 28d6 10/23/03 37.85(1.490) 36.58(1.440) pin 1 15.49(0.610) 12.95(0.510) 0.127(0.005)min 1.52(0.060) 0.38(0.015) 0.66(0.026) 0.36(0.014) 1.65(0.065) 1.14(0.045) 15.70(0.620) 15.00(0.590) 17.80(0.700) max 0.46(0.018) 0.20(0.008) 2.54(0.100)bsc 5.08(0.200) 3.18(0.125) seating plane 5.72(0.225) max 33.02(1.300) ref 0o~ 15o ref dimensions in millimeters and (inches). controlling dimension: inches. mil-std 1835 d-10 config a (glass sealed)
18 0007n?peepr?9/09 at28hc256 28.2 28f ? flatpack 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28f , 28-lead, non-windowed, ceramic bottom-brazed flat package (flatpack) b 28f 10/21/03 dimensions in millimeters and (inches). controlling dimension: inches. mil-std 1835 f-12 config b pin #1 id 9.40(0.370) 6.35(0.250) 0.56(0.022) 0.38(0.015) 1.27(0.050) bsc 1.14(0.045) max 3.02(0.119) 2.29(0.090) 1.14(0.045) 0.660(0.026) 7.26(0.286) 6.96(0.274) 1.96(0.077) 1.09(0.043) 0.23(0.009) 0.10(0.004) 10.57(0.416) 9.75(0.384) 18.49(0.728) 18.08(0.712)
19 0007n?peepr?9/09 at28hc256 28.3 32j ? plcc drawing no. rev. 2325 orchard parkway san jose, ca 95131 r title 32j , 32-lead, plastic j-leaded chip carrier (plcc) b 32j 10/04/01 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 e2 b e e1 e d1 d d2 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-016, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 3.175 ? 3.556 a1 1.524 ? 2.413 a2 0.381 ? ? d 12.319 ? 12.573 d1 11.354 ? 11.506 note 2 d2 9.906 ? 10.922 e 14.859 ? 15.113 e1 13.894 ? 14.046 note 2 e2 12.471 ? 13.487 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ
20 0007n?peepr?9/09 at28hc256 28.4 32l ? lcc 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32l , 32-pad, non-windowed, ceramic lid, leadless chip carrier (lcc) b 32l 10/21/03 dimensions in millimeters and (inches). controlling dimension: inches. mil-std 1835 c-12 11.63(0.458) 11.23(0.442) 14.22(0.560) 13.72(0.540) 2.54(0.100) 2.16(0.085) 1.91(0.075) 1.40(0.055) index corner 0.635(0.025) 0.381(0.015) x 45? 0.305(0.012) 0.178(0.007) radius 0.737(0.029) 0.533(0.021) 1.02(0.040) x 45? pin 1 1.40(0.055) 1.14(0.045) 2.41(0.095) 1.91(0.075) 2.16(0.085) 1.65(0.065) 7.62(0.300) bsc 1.27(0.050) typ 10.16(0.400) bsc
21 0007n?peepr?9/09 at28hc256 28.5 28s ? soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28s , 28-lead, 0.300" body, plastic gull wing small outline (soic) jedec standard ms-013 b 28s 8/4/03 dimensions in millimeters and (inches). controlling dimension: millimeters. top view side views 0.51(0.020) 0.33(0.013) 7.60(0.2992) 7.40(0.2914) 10.65(0.419) 10.00(0.394) 1.27(0.50) bsc 2.65(0.1043) 2.35(0.0926) 18.10(0.7125) 17.70(0.6969) 0.30(0.0118) 0.10(0.0040) 0.32(0.0125) 0.23(0.0091) 1.27(0.050) 0.40(0.016) 0o ~ 8o pin 1
22 0007n?peepr?9/09 at28hc256 28.6 28t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28t , 28-lead (8 x 13.4 mm) plastic thin small outline package, type i (tsop) c 28t 12/06/02 pin 1 0o ~ 5o d1 d pin 1 identifier area b e e a a1 a2 c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-183. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.90 1.00 1.05 d 13.20 13.40 13.60 d1 11.70 11.80 11.90 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.55 basic
23 0007n?peepr?9/09 at28hc256 28.7 28u ? pga 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28u , 28-pin, ceramic pin grid array (pga) b 28u 10/21/03 dimensions in millimeters and (inches). controlling dimension: inches. 13.74(0.540) 13.36(0.526) 15.24(0.600) 14.88(0.586) 2.57(0.101) 2.06(0.081) 7.26(0.286) 6.50(0.256) 1.40(0.055) 1.14(0.045) 0.58(0.023) 0.43(0.017) 3.12(0.123) 2.62(0.103) 1.83(0.072) 1.57(0.062) 14.17(0.558) 13.77(0.542) 12.70(0.500) typ 2.54(0.100) typ 16.71(0.658) 16.31(0.642) 2.54(0.100) typ 10.41(0.410) 9.91(0.390)
0007n?peepr?9/09 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support p_eeprom@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or co mpleteness of the contents of this document and reserves the ri ght to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. ? 2009 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others ar e registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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